Mitigation of Harmonics for Eleven-Level Cascaded Multilevel Inverter using SPWM and SHE Techniques

Abstract

Multilevel inverters became special attention in power electronics. The advantage of multilevel inverters is several levels of DC voltages are synthesized into a desired sinusoidal waveform. There are many topologies existed in literature like 1) Diode-clamped multilevel inverter, 2) Flying capacitor multilevel inverter, and 3) Cascaded multilevel inverter. First two topologies have a disadvantage of more number of components and gate driver circuits. This will lead to increase in losses and the total harmonic distortion is also more. So the quality of power is reduced. To overcome these drawbacks cascaded multilevel topology has been developed which is having less number of components and gate driver circuits. Thereby losses and THD (Total Harmonic Distortion) reduces and quality of power increases. The developed topology is analyzed for 11-level by using Phase Opposition Sinusoidal Pulse Width Modulation (PO-SPWM) Technique and also compared with novel SHE(Selective Harmonic Elimination) technique in terms of THD and quality of power for different modulation indices. The work is carried with MATLAB 2017b version.